Arteris Supercharges Chiplet Innovation with Expanded Multi-Die NoC IP Suite

With the explosion of AI workloads and edge computing driving demand for performance and power efficiency, chipmakers are increasingly turning to multi-die designs that combine different types of processors and accelerators on separate dies or chiplets. This design strategy not only improves scalability and yields but also reduces costs compared to traditional monolithic SoCs.

Arteris is capitalizing on this trend by upgrading its FlexNoC®, Ncore®, and Magillem® Connectivity IP and software offerings. These tools are now optimized to support both coherent and non-coherent inter-die communication, ensuring seamless connectivity across multiple chiplets and enabling SoCs to perform as if they were single-die solutions.

A key part of this upgrade is the enhancement of the Ncore cache coherent NoC, which now allows coherent read/write transactions between chiplets. This makes the multi-die SoC appear as a single, unified system to software, easing the burden on developers and improving runtime performance.

“The new capabilities address the critical design, integration, and verification challenges of multi-die systems,” said K. Charles Janac, CEO of Arteris. “By enabling software to treat chiplets as part of a monolithic system, we empower semiconductor teams to deliver faster innovation in AI, 5G, automotive, and data center markets.”

Additionally, Arteris has strengthened ecosystem alignment through support for industry-standard interconnect protocols such as UCIe, AMBA CHI, PCIe, and CXL. Collaborations with leading semiconductor and EDA companies like Synopsys, Cadence, Arm, Renesas, and TSMC further enhance the practical applicability of Arteris solutions in real-world SoC and chiplet projects.

Another vital component of the announcement is the enhanced Magillem SoC Integration Automation software, which allows designers to efficiently manage multi-die architectures by automating hardware/software interface description, register specifications, and IP-XACT metadata generation across dies.